Circuit and system fault tolerance techniques / Imran Wali ; sous la direction de Arnaud Virazel et de Patrick Girard

Date :

Type : Livre / Book

Type : Thèse / Thesis

Langue / Language : anglais / English

Tolérance aux fautes (informatique)

Architecture des réseaux d'ordinateurs


Électronique numérique

Virazel, Arnaud (1974-....) (Directeur de thèse / thesis advisor)

Girard, Patrick (1964-.... ; enseignant-chercheur en informatique) (Directeur de thèse / thesis advisor)

Alves de Barros Naviner, Lirida (19..-....) (Rapporteur de la thèse / thesis reporter)

Monteiro, Fabrice (Rapporteur de la thèse / thesis reporter)

Bosio, Alberto (19..-....) (Membre du jury / opponent)

Sonza Reorda, Matteo (Membre du jury / opponent)

Université de Montpellier (2015-2021) (Organisme de soutenance / degree-grantor)

École Doctorale Information, Structures, Systèmes (Montpellier ; 2015) (Ecole doctorale associée à la thèse / doctoral school)

Laboratoire d'informatique, de robotique et de micro-électronique (Montpellier ; 1992-....) (Laboratoire associé à la thèse / thesis associated laboratory)

Résumé / Abstract : Non traduit

Résumé / Abstract : Semiconductor is one of the most reliable inventions when engineered and used with longevity in mind. However, the increasing demand of fast and highly featured products has drastically changed the reliability realm in the recent years. The means of improving the reliability of nano-metric technology circuits encompass techniques that tackle reliability issues at the level of technology, design and manufacturing. Absolutely necessary but these techniques are almost inevitably imperfect. Therefore, it becomes essential to reduce the consequence of the "remaining" faults using fault tolerance techniques.This thesis focuses on improving and developing new low-power fault tolerance techniques that combine the attractive features of different types of redundancies to tackle permanent and transient faults and addresses the problem of error detection and confinement in modern microprocessor cores. Our case study implementation results show that a power saving of up to 20% can be achieved in comparison with fault tolerance techniques that use only one type of redundancy, and offer low-power lifetime reliability improvement.With the objective to further improve the efficiency in terms of cost and fault tolerance capability we present a design space exploration and an efficient cost-reliability trade-off analysis methodology to selectively harden logic circuits using hybrid fault tolerant techniques. The outcome of the two studies establish that hybrid fault tolerant approaches provide a good foundation for building low-power reliable circuits and systems from future technologies, and our experimental results set a good starting point for further innovative research in this area.