Date : 2007
Type : Livre / Book
Langue / Language : anglais / English
ISBN : 978-3-540-74442-9
Circuits intégrés à très grande échelle
Systèmes informatiques -- Pannes
Circuits intégrés -- Conception assistée par ordinateur
Unités arithmétiques et logiques
Classification Dewey : 621.395
Classification Dewey : 004
Collection : Theoretical computer science and general issues / Berlin : Springer , [2006?]-
Résumé / Abstract : th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.